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gcc
options for architecture and code generation for Hitachi SH
-mshl
Generate little-endian Hitachi
SH coff output.
-m1
Generate code for the Hitachi
SH-1 chip. This is the default behavior for the Hitachi SH configuration.
-m2
Generate code for the Hitachi
SH-2 chip.
-m3
Generate code for the Hitachi
SH-3 chip.
-m3e
Generate code for the Hitachi
SH-3E chip.
-mhitachi
Use Hitachi’s calling convention
rather than that for gcc.
The registers MACH
and MACL
are saved with this setting (see Calling
conventions for Hitachi SH).
-mspace
Generate small code rather
than fast code. By default, gcc
generates fast code rather than small code.
-mb
Generate big endian code.
This is the default.
-ml
Generate little endian code.
-mrelax
Do linker relaxation. For
the Hitachi SH, this means the jsr
instruction can be converted to the bsr
instruction. -mrelax
replaces the obsolete option -mbsr.
-mbigtable
Generate jump tables for
switch statements using four-byte offsets rather than the standard two-byte
offset. This option is necessary when the code within a switch statement
is larger than 32k. If the option is needed and not supplied, the assembler
will generate errors.
Floating point subroutines for Hitachi SH
Two kinds of floating point subroutines are useful with GCC.